This page is a quick summary, of limits both physical, and technology related, that affect computer technology.
As a simple to remember value 3x108 or 300,000,000 meters per second. That works out as approximately 1 foot, per nano second, or 1000,000,000 feet per second.
It has odd implications for just about all of our modern technology.
These are where the initial designers pick arbitrary values, as part of the design process. These are picked on the basis that they will be adequate for all foreseen uses.
First snag is that technology often moves faster than the designers thought. Second snag is that when you out grow the limit, changing a standard after it has been embedded in lots of devices can be a real pain.
ST506 disk controllers addressed drives in terms of head, cylinder, and sector.
This addressing scheme was carried over to the early IDE drives and the original DOS partition table.
| head | Identified the head for the data, range 1 to 16 |
| cylinder | Data recorded in concentric rings on the disk, with a stack of platters, the set of sectors the same distance out from the spindle form a cylinder. Range is 1 to 1024. |
| Sector | smallest block of data, that can be updated, the sectors are arranged around the disk with small gaps between. Sectors around the track are logically numbered from 1 to a maximum of 63. They may not be in numerical order. |
The above addressing scheme is limited to 1,048,576 sectors, so assuming 512 Byte per sector this addressing scheme is limited to 528 MB.
Sectors are treated as a single dimensional ordered list. Simplifies programming but hides the physical structure of the drive. OS has less chance to optimise request order.
| 22 bit | 2 GB | Original IDE standard |
| 28 bit | 128 GB | ATA-1 1994 |
| 48 bit | 128 EB | ATA-6 2003 |
Random access speed for rotational storage, has mainly been determined by two factors the seek time to the right track, and the time spent waiting for the drive to rotate, to bring the required sector to the heads. Chance says that once the head arrives at the desired cylinder, you will on average be half a rotation from the sector you want.
| RPM | One rotation ms | half rotation | Seek | Total | TPS |
|---|---|---|---|---|---|
| 3,600 | 16.66 | 8.33 | 6 | 14.33 | 70 |
| 5,200 | 11.54 | 5.77 | 5 | 10.77 | 93 |
| 7,200 | 8.33 | 4.16 | 4 | 8.16 | 122 |
| 10,000 | 6.00 | 3.00 | 2 | 5 | 200 |
| 15,000 | 4.00 | 2.00 | 2 | 4 | 250 |
Technically it is possible to use a sightly smaller disk in a drive, in conjunction with two or three heads. this gives the possibility of accessing two different tracks at the same time, or picking the head to minimize rotational latency. Snag is that puts up complexity and manufacturing costs.
Solid state storage on the other hand has a very short address set-up time, and it makes no difference where the sector that is wanted is located. Generally the flash modules will cope with 50,000 random 4 KB reads per second. which works out as 200 MB/s.
As of 2016 best controllers can make parallel request to multiple banks of flash modules, returning 100,000 or more read operations per second.
Write operations are more problematic, erasing a flash cell is comparatively slow. For best performance you configure the controller to report a virtual drive, that is significantly smaller than the total flash fitted. This excess is pre erased, and available for incoming write requests. As it is used for new data, the storage with the old data, is queued for an erase operation.
A file system that supports trim can disown chunks of data that it is no longer interested in, the drive can add these to the erase queue. With a stock of pre erased data blocks a flash based drive can perform random writes at about half the random read rate. If it runs out of pre erased blocks write speed will drop to around a tenth of that. which is still 10 times faster than the best rotating disks can manage for random I/O.
As of 2018 a good RAID controller can yield higher sustained linear write speed than a SSD.
SSD capacity is directly tied to the chip manufacturing precesses. As the manufacturing process has been refined, and the minimum feature size reduced, so the capacity per chip has gone up. Snag is that the smaller the storage cells, the less charge that has to leek in or out of the cell to change the value stored.
While a storage device is powered it is possible for it to read back blocks of memory, and check the number of bit errors, against the error correction scheme used, then rewrite data before it gets lost. If a device is going to be powered off for extended periods this is a very important consideration.
Cells have a limit to how many times they can be erased and re written. in a server application involving lots of updates to say a database, this can be the most important consideration.
As of 2017 there are 4 different cell designs in use with different costs, and properties.
| SLC | Single Level Cell, each cell takes one of two state, charged/discharged. Long life 100,000 program/erase cycles, and long data retention while powered off. Limited capacity for a given chip area. Therefore a high cost per GB. |
| TLC | Triple Level Cell, each cell can be changed to three different voltage levels. |
| MLC | Multi Level Cell, each cell can be changed to a number of different voltage levels. |
| eMLC | Extended life. Design increases some of the spacings to decrease leakage, and allows for far more write cycles, allowing drive endurances of 10 to 20 writes per day. |
Note a multi level cell, does not store bits it stores symbols. If it takes 3 values then a group of such cells are effectively storing base 3 values. with 4 voltage levels you are storing base 4 values. In all cases the controller has the job of taking your data, running it through a forward error correction scheme, then converting to an appropriate number base for the cell type and storing. If it gets it right it can read the group of cells at a later time and reconstruct your data, even if a couple of the cells used have drifted up or down a level.
I am unclear on what TLC actual stores, from its name you would take it to be 3 voltage levels on each cell, but many references suggest it is storing 3 bits which would take 8 voltage levels.
The heads in hard drives share many manufacturing details with chip manufacture, so as chip feature sizes have shrunk, so has the head size of hard disks. A complication is that there are physical constraints as well. How ever there have been a number of changes over the years. The result is that drive capacity change shave not been as smooth as scaling in computer memory densities.
| Type | Comment | Physical limit 3.inch platter |
|---|---|---|
| Linear FM recording | ||
| Linear MFM recording | 40% jump in capacity, same heads. | 250 GB |
| Perpendicular recording | Thicker recording layer, with backing layer. | 1.5 TB |
| Heat Assisted Magnetic Recording (HAMR) | Spot heat surface with laser, so dipole may be flipped with a weaker field. | ? |
| Microwave Assisted Magnetic Recording (MAMR) | Spot heat surface with microwave, so dipole may be flipped with a weaker field. | ? |
Historical trend is for capacity to grow for a number of years, followed by a switch to smaller faster platters. 2.5 inch drives for example have smaller platters and less of them, giving about a fifth of the capacity of a 3.5 inch drive using the same head technology.
| 1963 | IBM 1311, 6 14 inch platters, 2.6 MB | |
| 1979 | IBM 3370, 7 14 inch platters, 571 MB | |
| 1979 | IBM 62, 6 8 inch platters, 64 MB | |
| 1983 | Rodime RO352 2 3.5 inch platters 10MB. | |
| 1988 | 2x2.5inch platters 20MB | |
| 1991 | 1x 1.8inch platter, 21 MB | |
| 1992 | Segate Baracuda, 7200 rpm, 3.5 inch, 2.1 GB | |
| 1997 | IBM introduces GMR head, giving 16.8 GB, on 5 3.5inch platters | |
| 2006 | PMR | segate 3.5 inch perpendicular recording, 750 GB |
| 2006 | PMR | toshiba 2.5 inch perpendicular recording, 200 GB |
| 2008 | PMR | 1.5 TB |
| 2010 | PMR | 3 TB |
| 2011 | PMR | 4 TB |
| 2013 | PMR | 5 TB |
| 2014 | PMR | 8 TB |
| 2015 | PMR | 10 TB |
| 2017 | PMR +helium | 12 TB |
| 2018 | PMR +helium | 14 TB |
| 2018 | HAMR | 16 TB |
| 2020 | HAMR | 20 TB |
| 202? | MAMR | 40 TB |
| 2032 | MAMR | 100 TB |
Mid 2016 a 5 TB hard disk, and a 500 GB solid state drive were priced similarly. Latest hard disk are approaching the physical limits for perpendicular recording using magnetic domains. Pending another technical break trough, I would expect capacity to plateau, while prices decline.
There is room within the known technical limits for further capacity growth, and reductions in cost per GB.
First server drives, with integrated controllers. Drives often did not have a fixed geometry. The outer and therefore longer tracks could be formatted with more sectors.
The SCSI command set used a logical sector address.
Shrink the electronics for controlling the disk, and fit to the bottom. Uses a standardised cable to connect to the MB. Simplifies design and avoids the need to allocate an expansion slot for a disk controller.
Original IDE solution using a 40 way cable, with signalling modelled on 16 bit AT bus.
http://en.wikipedia.org/wiki/Parallel_ATA
Drive addressing and consequent capacity has been revised several times.
| Up till | Maximum Capacity | Limitation |
|---|---|---|
| 1994 | 528 MB | IDE PIO mode using head Cylinder Sector addresses. BIOS limit of 1024 cylinders, 16 heads, and 63 sectors. |
| 1996 | 2.1 GB | chip set 430FX, allowed for more cylinders? |
| ? | 8.4 GB | MSDOS and Windows 95 bug limiting CHS addressing to 1024 cylinders, 255 heads, and 63 sectors. |
| 1999 | 32 GB | UDMA mode, using LBA with 26 bit address. |
| 2001 | 137 GB | Chipset and or BIOS and or Drive 28 bit LBA addressing limit. BIOS limit did not apply to add on controller cards. |
| ? | + | There are multiple reference around that Windows 98 did not support 48 bit addressing, however I have run Win 98 with an ATA-133 add in card and a 250GB ATA drive as two 125GB FAT32 partitions. |
| + | + | ATA-6, on wire support for 48 bit LBA addresses. |
NoteDOS partition table even in LBA mode, is limited to 32 bit LBA addresses. Running at 512 byte sectors that works out at 2 TB.
Speed peeked at 133 MB/s for ATA133 UDMA, as against the original 3.3 MB/s for PIO Mode 0.
Collaboration between Western Digital, CDC, and Compaq. Software interface retained compatibility with the existing ST-506 drive interface.
Added an identify device command, that will return the device details, from a compliant device. This allows the BIOS to auto detect devices and their capabilities at boot time.
Development to allow other block devices to use the motherboard ATA interface. This is implemented by allowing the ATA interface to carry SCSI commands.
The SCSI command set supports alternate block sizes, used with CDROM, and tape drives.
Added S.M.A.R.T. reporting of drive health.
Added single 44 pin power and data cable for 2.5 inch drives.
Faster transfer of between 16 MB/s and 33 MB/s.
ATAPI support.
Faster 66 MB/s transfer option. Using an 80 core ribbon cable, with a earth wire between each data signal.
48 bit LBA addressing.
Hybrid drive support, where drive contains both conventional magnetic storage, and a small amount of flash memory to provide fast access to some data.
IBM drive connection technology from the 1990s. Ran the SCSI command set over a high speed serial network with a ring topology. Ring is bidirectional dual channel. Maximum aggregate data rate 80 MB/s. Maximum of 192 hot swappable drives. Shared between multiple server interface cards.
At its simplest a ring topology like SSA. But it supports agregators and switches, to form a fault tolerant multipath mesh.
| year> | Speed | encoding | throughput |
|---|---|---|---|
| 1 Gbit | 8b10b | 103.2 | |
| 2 Gbit | 8b10b | 206.5 | |
| 4 Gbit | 8b10b | 412.9 | |
| 8 Gbit | 8b10b | 825.8 | |
| 10 Gbit | 64b66b | 1,239 | |
| 16 Gbit | 64b66b | 1,652 | |
| 32 Gbit | 64b66b | 3,303 |
Has similarities to SATA see below, but drive connector has a few extra contacts. It is possible in many cases to attach a SATA drive to a SAS controller. Topology is like a snow flake. An 8 channel controller could control 8 drives, but you could wire 1 or more channels to a fanout controller that supports say 24 device channels.
There is a performance implication when using fan out controllers, depending on drive seek times, buffering, and command queues.
Replaces 40 way ribbon cable with a two pair connection, running one pair in each direction, clocked at 1.5GHz with an 8/10 forward error correction expansion. This gives a full duplex data rate of 150 MB/s.
Command set is ATA-6, with the same theoretical limits. A simple in line converter can convert to ATA-133 signalling on a 40 way cable, to allow existing ATA-133 drives to be used on a mother board with SATA connections.
Intel chipsets i865, and i875, provided for two SATA connections, VIA KT-600 supported 4?
Double speed version of SATA being clocked at 3GHz for a 300 MB/s transfer rate.
Drives should detect if connected to a slower SATA interface, though some drives needed a jumper setting.
Note the following SATA1 controller chipsets, are known not to auto negotiate speed with SATA2 drives.
Double speed version of SATA2 being clocked at 6GHz for a 600 MB/s transfer rate.
Drives should detect if connected to a slower SATA, or SATA2 interface, though some drives needed a jumper setting.
Methods for connecting peripheral devices to computer.
Initial version could operate in two modes:-
Interface could supply power to devices such as a mouse, or keyboard that had low power requirements.
New high speed mode, offering 480 Mbps, or 60 MB/s. Confusingly not all USB2 devices support the new speed.
Practical speed limit for sequential block I/O to or from a fast storage device seems to be around 35 MB/s.
Ports on a computer or powered hub can provide 500mA at approximately 5V. same as for USB 1.
New super speed mode, offering 5 Gbps, or 625 MB/s. Protocol changes to reduce work for CPU. It is very unlikely that any available device will reach close to the theoretical top speed.
One possibility is to use the USB 3 interface standard instead of HDMI, or display port for connecting a display device.
Ports on a computer or powered hub will provide 900mA at approximately 5V, to any device.
USB Power Delivery specification, a compliant device can ask the host to change the supply voltage or current limit. Up to 20 volt, and 5 amp. host may decline the request.
Roll up of engineering revisions since 3.0 in to a consolidated document.
This is not a revision to the USB protocols it is a new socket design, that is making its first appearance as a new connector for USB. It is a symmetric socket, using differential signalling, plug can be flipped 180 degrees and still fit. Can be used at either USB host, or USB device end.
Supports USB power delivery standard 2, with up to 20V and 5 A. Key difference is that the cable is symmetric, so devices negotiate as to which is the power source.
May be used with any of the USB protocol standards. Connector has extra pins that allow for a few other use cases.
If my understanding is correct the extra pins add 3 additional channels. so 4 channels at 10 Gbit each using current signalling standards. Whether these are used will depend on the cable used, and the connected devices.
Theoretically a device can have a type "C" socket, and switch it between being
So a small device like a mobile phone, or camera, could have one type "C" socket, and a couple of cables. To change, show high definition photos on that 4K or 8K display, backup to your home server, load a movie from your DVR, or many other uses.
New super speed mode, offering 10 Gbps, or 1.25 GB/s. Protocol changes to reduce work for CPU. It is very unlikely in the short term that any available single device will reach close to the theoretical top speed.
This is similar to USB but exists as an open IEEE standard, and was faster.
Designed by Intel, and mostly used on Apple devices.
Change of socket design to the USB type "C" connector used with USB 3.1.
Theoretical top speed of 40 Gbps, 5 GB/s.